1. Field of the Invention
The present invention relates to a data transfer controller, a data consistency determination method and a storage controller.
2. Description of the Related Art
A storage controller, for example, is connected to a server, mainframe, or other such host computer (hereinafter, “host”). The storage controller provides the host with a storage area based on RAID (Redundant Array of Inexpensive Disks).
In the storage controller, for example, it is also possible to add redundancy to data, in levels known as RAID 1 through RAID 6. The storage controller prepares for a disk drive failure by either adding parity to data, or writing a copy of the data to a different disk drive.
Furthermore, a storage controller that uses a guarantee code is also known (JP-A-2000-347815). In one prior art, the host computer respectively adds to a logical block as the guarantee code the logical address (hereinafter, “LA (Logical Address)”) of the logical block specified as an access destination, and an LRC (Longitudinal Redundancy Check) determined by implementing an exclusive OR operation for the data of the logical block, and saves this guarantee code and logical block to a disk drive. The LA is used to detect an address error in a storage area into which the data of the logical block is written. The LRC is used as an error detection symbol for detecting an error in the logical block data.
However, there may also be situations in which data is not transferred to a cache memory in order. A disorderly transfer state like this is called out-of-order. A method for properly configuring guarantee codes in the respective logical blocks even when an out-of-order state occurs has been proposed (JP-A-2006-40011). Furthermore, a technology related to a memory error correction symbol is also known (JP-A-2007-115390).
In the prior art, a guarantee code can be configured in the logical block even when an out-of-order state occurs. However, this prior art only discloses the guarantee code configuration method; there is absolutely no mention of a method for determining whether or not all data has been transferred to cache memory normally. Therefore, the prior art lacks usability in that it does not make it possible to accurately determine whether or not all the data that should be transferred and stored in cache memory has been received.